The use of CMOS circuits has become widespread. In an approach referred to as static CMOS, except during switching, the output is connected to either the positive supply voltage or the negative supply voltage through a low resistance path. In an approach referred to as dynamic CMOS, the output may rely on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Currently, high speed XOR designs have mainly concentrated on a pass gate type of logic circuits, a dynamic CMOS approach. Such a design has a lesser transistor count, but will not work well at low voltages because pass gates could have a VT drop between the drain and source. As the technology shrinks, threshold voltage is becoming increasingly comparable to the supply voltage. Therefore, conventional circuit styles are increasingly risky on achieving reliable high speed operation.
In the conventional static CMOS XOR, the worst case path is when the PMOS closest to VDD has to pull up all the nets up to the lowermost NMOS which is closest to VSS (the same path exists for pull-down from the lowermost NMOS to the uppermost PMOS). This results in very slow transitions, especially at low voltage operation.
Background information may be found in Kuo-Hsing Cheng and Ven-Chieh Hsieh, “High Efficient 3-input XOR for Low-Voltage Low-Power High-Speed Applications,” AP-ASIC '99, IEEE, 1999, pp. 166-169.
Further background information may be found in U.S. Pat. No. 4,417,161.